1. Field of the Invention
The present invention generally relates to liquid crystal display technology, and more particularly to the pixel structure of a liquid crystal display having balanced parasitic capacitance.
2. Description of the Related Art
Conventionally, the structure of a thin film transistor liquid crystal display (TFT-LCD) includes a TFT array substrate, a color filter array substrate, and a liquid crystal layer sandwiched between the TFT substrate and the color filter substrate. The TFT substrate conventionally carries an array of thin film transistors, each of which is connected to one pixel electrode. Each thin film transistor operates as a switch element to apply a voltage to the pixel electrode, which thereby creates an electric field in the liquid crystal layer to selectively control the orientation of the liquid crystal molecule director for displaying images.
FIG. 1A is a schematic view of a pixel area in a conventional active matrix liquid crystal display. In the pixel area, a thin film transistor 10 is conventionally coupled with a data line 32 and a scan line 42. The thin film transistor 10 includes a gate electrode 12 connected to the scan line 42, a source electrode 14 connected to the data line 32 and a drain electrode 16 connected to a pixel electrode 50. The source electrode 14 and drain electrode 16 are formed over a semiconductor layer 6. Another data line 34 runs along a side of the pixel electrode 50 opposite to the side of the coupled data line 32.
FIG. 1B is a cross-sectional view taken along section 1B in FIG. 1A. The pixel structure including the thin film transistor 10 is usually formed over a substrate 2. The data lines 32, 34 are formed on a gate-insulating layer 4 covering the gate electrode 12. The pixel electrode 50 is formed on a dielectric layer 8 that covers the substrate 2, including the thin film transistor 10 and the data lines 32, 34. In this conventional pixel structure, the proximity of the data lines 32, 34 at two sides of the pixel electrode 50 produces a parasitic capacitance. Since the pixel electrode 50 has two capacitive coupling sides of different length, the resulting capacitive coupling (Cpd1, Cpd2) with the data line 32, 34 conventionally differs at the two sides of the pixel electrode 50, i.e. Cpd1≠Cpd2. This differential parasitic capacitance results in a fluctuation of the operating voltage of the pixel electrode 20, which generally causes pixel flickering and cross talk effects.
To solve the problems of parasitic capacitance in pixel structures, many technical approaches are known in the art.
FIG. 1C illustrates a conventional pixel structure configured to reduce the parasitic capacitance between a light-shield film and the source/drain electrodes of the thin film transistor as described in U.S. Pat. No. 5,745,194, the disclosure of which is incorporated herein by reference. The illustrated thin film transistor is covered with a light-shielding layer 60. A compensation capacitor 40 is further formed in an area overlapping the pixel electrode 50 and the data line 34 uncoupled with the pixel electrode 50 to compensate their mutual capacitive coupling.
U.S. Pat. No. 5,886,757 describes a liquid crystal display having thin film transistors of reduced parasitic capacitance, the disclosure of which is incorporated herein by reference. In this reference, one thin film transistor includes a gate electrode extending from one scan line, a drain electrode connected to a pixel electrode, and a source electrode connected to a data line. The source electrode has a width greater than the width of the drain electrode to reduce a parasitic capacitance of the thin film transistor.
In U.S. Pat. No. 5,614,427, the disclosure of which is also incorporated herein by reference, the drain electrode is configured to completely surround the source electrode of the thin film transistor. This particular geometry enables to reduce the parasitic capacitance of the thin film transistor.
U.S. Pat. No. 5,414,283 also discloses a thin film transistor implemented in a liquid crystal display with reduced parasitic capacitance. In this reference, a thin film transistor includes a central rounded source electrode that is surrounded by an annular or circular drain electrode to reduce the parasitic capacitance.
The aforementioned approaches known of the prior art may bring some solutions to the issue of parasitic capacitance, but are not economical when practically put in implementation. In particular, the design of specific geometry of the thin film transistor requires a high precision patterning process and reduces the window process. As a result, the manufacture cost is increased.
Therefore, there is presently a need for a liquid crystal display that can reduce the undesirable effects caused by the parasitic capacitance in the pixel structure, and be economically put in production without increasing the manufacture cost.